The present invention relates to a semiconductor memory device, in particular, to technology which is effective when applied to a semiconductor memory device which includes an SRAM.
An SRAM (Static Random Access Memory) is a kind of a semiconductor memory, and stores data by use of a flip-flop. For example, in an SRAM, data (“1” or “0”) is stored in two cross-coupled CMOS inverters configured with four transistors. Since two transistors are needed additionally for a read and write access, a memory cell of a typical SRAM is configured with six transistors.
For example, Patent Literature 1 (Published Japanese Translation of PCT International Publication No. 2006-527897) cited below discloses a nonvolatile static memory cell in which a nonvolatile cells (14, 16) are cross-coupled to internal nodes (A, B) of the static memory cell. One nonvolatile cell (14) of the two nonvolatile cells has a control gate coupled to B and a source coupled to A, and the other nonvolatile cell (16) has a control gate coupled to A and a source coupled to B.
Patent Literature 2 (Published Japanese Unexamined Patent Application No. Hei 7 (1995)-226088) cited below discloses a semiconductor memory device which can realize a nonvolatile property while maintaining speediness of a static memory (SRAM). This semiconductor memory device has an SRAM memory cell unit 1 and a nonvolatile memory cell unit 3. The SRAM memory cell unit 1 is configured by coupling a first and a second selection transistor T7 and T8 to two transistors T1 and T2, of which the respective sources are grounded and the respective drains are coupled to each other's gates. The nonvolatile memory cell unit 3 is configured with nonvolatile transistors T3 and T4 which are provided with two gates, a floating gate and a control gate, and the drains coupled to a power supply line, thereby storing the state of the SRAM memory cell unit 1.
Patent Literature 3 (Published Japanese Translation of PCT International Publication No. 2003-511809) discloses a nonvolatile MOSRAM cell configured with a first and a second inverter and capacitors (G1, G2) each coupled in series to a control electrode of each of the first and the second inverter.
Patent Literature 4 (Published Japanese Unexamined Patent Application No. 2007-157183) cited below discloses a nonvolatile memory configured with a flip-flop which comprises a pair of series circuits of a load transistor and a memory transistor, coupled in a static latch mode. This nonvolatile memory is provided with leakage-current cutoff elements (T16, T26) coupled to a current path through which a leakage current flows into the power supply side of the flip-flop via the load transistor in writing and erasing.
Patent Literature 5 (Published Japanese Unexamined Patent Application No. Hei 6 (1994)-76582) cited below discloses a nonvolatile memory which stores information by changing a threshold voltage of field effect transistors (RMmn (o+), RMmn (o−)) which act as a pair of flip-flops of a memory cell.
Patent Literature 6 (Published Japanese Unexamined Patent Application No. Hei 7 (1995)-183401) cited below discloses a nonvolatile memory cell which comprises four N-channel MOS transistors and two P-channel TFTs as load elements. The TFT has a laminated structure comprised of a first TFT gate electrode 9 in a lower layer, a TFT gate insulating film 10, a body layer (semiconductor layer) 13 which forms a channel of the TFT, a second gate insulating film 22 which has ferroelectricity, and a second TFT gate electrode 23.
Patent Literature 7 (Published Japanese Unexamined Patent Application No. 2004-207282) cited below discloses a nonvolatile SRAM cell which comprises a pair of two cross-coupled CMOS inverters c1 and c2 and ferroelectric capacitors fc1 and fc2. The ferroelectric capacitors fc1 and fc2 are formed respectively by lower electrodes BEL1 and BEL2, ferroelectric films FER1 and FER2, and upper electrodes TEL1 and TEL2, the lower electrodes BEL1 and BEL2 being respectively coupled to a drain diffusion area included in corresponding one of the two CMOS inverters.
Non Patent Literature 1 cited below discloses a nonvolatile SRAM cell which has NVM devices (XR1, XR2) coupled between two storage nodes of the SRAM and a control line (ctrl).
Non Patent Literature 2 cited below discloses a nonvolatile SRAM which has two SONOS transistors as a memory device. The SONOS transistors are coupled respectively between two storage nodes of the SRAM and a VCCT line.
(Patent Literature 1) Published Japanese Translation of PCT International Publication No. 2006-527897
(Patent Literature 2) Published Japanese Unexamined Patent Application No. Hei 7 (1995)-226088
(Patent Literature 3) Published Japanese Translation of PCT International Publication No. 2003-511809
(Patent Literature 4) Published Japanese Unexamined Patent Application No. 2007-157183
(Patent Literature 5) Published Japanese Unexamined Patent Application No. Hei 6 (1994)-76582
(Patent Literature 6) Published Japanese Unexamined Patent Application No. Hei 7 (1995)-183401
(Patent Literature 7) Published Japanese Unexamined Patent Application No. 2004-207282
(Non Patent Literature 1) Wei Wang et al; “Nonvolatile SRAM Cell”, 1-4244-0439-8/06/$20.00(c) 2006 IEEE
(Non Patent Literature 2) Michael Fliesler et al; “A 15ns 4 Mb NVSRAM in 0.13u SONOS Technology”, 987-1-4244-1 547-2/08/$25.00 (c) 2008 IEEE PP. 83-86